A complementary MOS (CMOS) semiconductor device includes an N-channel MOSFET (NMOSFET) device and a P-channel MOSFET (PMOSFET) device which are fabricated on and in a semiconductor substrate. The semiconductor substrate can generally be either a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate. A SOI substrate generally includes at least one thin layer of semiconductor material disposed on or over a buried oxide insulating layer which, in turn, is supported by a carrier wafer so that the buried oxide insulating layer is disposed between the carrier wafer and the semiconductor layer.
The performance of a CMOS semiconductor device can be measured in terms of switching speed and operational frequency which are proportional to the mobility of charge carriers, electrons or holes, in a given CMOS semiconductor device. The mobility of the majority charge carrier depends directly on a crystallographic orientation of the semiconductor substrate in and on which the CMOS semiconductor device is fabricated. For example, the majority carrier in NMOSFET devices are electrons, and the mobility of electrons is best in semiconductor materials having a (100) crystallographic orientation. As such, the optimal crystallographic orientation for NMOSFET devices is (100) since this allows for the highest electron mobility. By contrast, the majority carrier in PMOSFET devices are holes, and the mobility of holes is best in semiconductor materials having a (011) or equivalent crystallographic orientation. Therefore, the optimal crystallographic orientation for PMOSFET devices is (011) or equivalent crystallographic orientation since this allows for the highest hole mobility. The (101) and (011) crystallographic orientations are equivalent to the (011) crystallographic orientation.
To improve performance and speed of CMOS devices, it would be desirable to provide a semiconductor substrate which has one crystallographic surface orientation for PMOSFET devices and another crystallographic surface orientation for NMOSFET devices. One approach for fabricating such a semiconductor substrate begins with a SOI substrate which has a thin silicon layer of a first crystallographic orientation (e.g., a (100) crystallographic orientation), and a silicon carrier wafer which has a second crystallographic orientation (e.g., a (011) crystallographic orientation). A trench is then etched through the thin silicon layer and the buried oxide layer until the carrier wafer is reached. Dielectric spacers are formed on the sidewalls of the trench. A selective epitaxial growth process is then used to selectively grow an epitaxial layer of silicon from the bottom of the trench to fill the trench with epitaxially-grown silicon material. The dielectric spacers prevent epitaxial growth from occurring from at potential nucleating sites on the sidewalls of the trench by covering those potential nucleating sites, and no epitaxial growth occurs on the dielectric spacer material. As a result, the selective epitaxial layer replicates the crystallographic orientation of the carrier wafer along of the bottom surface of the trench, and the selective epitaxial layer will ideally have a second crystallographic orientation that is identical to that of the carrier wafer. In theory, the resulting SOI substrate will have silicon regions with differentially oriented crystallographic surface orientations: one silicon region having a first (100) crystallographic orientation and another silicon region having a second (011) crystallographic orientation.
Unfortunately, this approach suffers from drawbacks which have prevented its use. For example, as the epitaxial layer is grown upwards in the trench from the carrier wafer, the epitaxial layer encounters dielectric spacers which disrupt the epitaxial growth process and cause defects in the crystallographic pattern of the silicon material. As a result, the crystallographic structure of the epitaxial layer does not precisely replicate the crystallographic pattern of the carrier wafer, and the epitaxial layer exhibits a high density of crystal defects as well as facets at the edges of the selective epitaxial layers. The defects in the crystalline structure of the epitaxial layer tend to degrade device performance.
In addition, the process of fabricating the SOI substrate using this approach involves a relatively complex series of steps. For example, to prevent epitaxial growth on the thin silicon layer, a capping layer must be formed on the thin silicon layer before the trenches are formed. An additional dielectric layer is then deposited on top of the capping layer and within the trench. It is used to form the dielectric spacers on the trench sidewalls to ensure that epitaxial growth does not occur at the edges of the thin silicon layer residing near the trench.
Accordingly, it is desirable to provide improved methods for fabricating a semiconductor substrate that includes silicon regions with differentially oriented crystallographic surface orientations. In addition, it is desirable to provide methods for fabricating CMOS devices on such semiconductor substrates. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.